This invention relates in general to semiconductor devices and more specifically to vertically oriented CMOS transistors having an isolated transistor overlying a bulk transistor.
In the design and fabrication of a memory component such as an SRAM cell it has been demonstrated that a CMOS transistor configuration operates with less quiescent power dissipation than for example, a cell using a polysilicon load resistor. A P-channel transistor, in the off state, can easily yield a resistance value three orders of magnitude greater than a polysilicon load resistor of suitable size for a VLSI-SRAM cell. Recently, vertically-oriented CMOS transistors have been developed that place the P-channel transistor in an overlying polysilicon layer. A vertical or stacked configuration offers the potential advantage of low power dissipation and high packing density. In a stacked configuration, the N-channel transistor and the P-channel transistor can use the same portion of a polysilicon lead as a gate electrode. This is known in the art as a shared gate. Each transistor channel is adjoined to a single portion of a polysilicon lead which results in a reduction in the amount of polysilicon required to form the CMOS gate and a further increase the packing density. Typically the source and drain of the N-channel transistor are formed in a bulk silicon substrate and the P-channel transistor is formed in an overlying layer of polysilicon which is electrically isolated from the substrate by an intermediate dielectric layer. Both the N-channel or bulk transistor and the P-channel or isolated transistor are switched on and off by applying a potential to the shared gate.
One problem associated with using an electrically isolated P-channel transistor in a shared gate configuration is the poor gain and switching performance generally obtained from the electrically isolated P-channel transistor. Obtaining optimum dynamic performance from the P-channel transistor requires critical attention to interface charge states facing the channel because of the inherent low charge carrier mobility in a semi-amorphous material such as polysilicon. The low carrier mobility increases the threshold voltage creating a need for more applied voltage to deplete the channel region. Also, because the P-channel transistor elements located in the overlying polysilicon layer are electrically isolated from the substrate, a convenient means of reverse biasing the source and drain junctions and the channel region is not available. The floating potential of the channel region causes variations in the threshold voltage of the isolated transistor and a reduction of the transconductance when the channel is saturated. Given the required switching speed, a sufficient voltage to invert the channel may not be applied in time to meet the switching requirement. This results in a low drive current in the CMOS transistor.
SRAM cells must store data in the form of a voltage difference and provide such difference across a bit line pair. The ability to rapidly establish the voltage difference on a bit line pair is dependent upon available drive current within the cell. The fabrication of an SRAM cell incorporating stacked CMOS transistor architecture has successfully reduced the SRAM cell area, however, these cells have also exhibited poor performance. SRAM cells using stacked shared gate P-channel load devices exhibit soft bit failure as a result of the P-channel not supplying sufficient current when the CMOS transistor is turned on. Accordingly, a need existed for a stacked shared gate CMOS transistor having an isolated transistor with improved gain and switching performance.